RISCV Instruction Set

It's a 32-bit processor:

• Word size is 32 bits.
• Max amount of bits that can be sent/received by memory is 32.
• Number of addressable locations in memory = 2³².

But memory is byte addressable (every byte gets sent to a separate address, 4 bytes at 4 separate addresses).

Words are stored in addresses divisible by 4. For example:

• t0 = 0(t0) → Address 0x2c
• next word: 4(t0) → Address 0x30
• next word: 8(t0) → Address 0x34
• next word: c(t0) → Address 0x38

Initializing memory with values: Assembler directives begin with a dot (.). Some examples:

• .word 10 → Puts a word size of 10 in the memory. Word is 4 bytes.
• .byte 50 → Puts 50 in the next byte.
• .hword 20 (half word) → Puts 20 in the next 2 bytes.

If we didn't have labels, we would have to figure out what the numbers for the actual addresses are (that change every time we insert/delete something in the program)

.global _start
_start:
    # Load immediate values into registers
    li a0, 10        # a0 = 10
    li a1, 20        # a1 = 20

    # Load values from memory
    la a2, var1      # Load address of var1 into a2
    lw a3, 0(a2)     # Load value at var1 into a3 (a3 = 10)
    
    la a2, var2      # Load address of var2 into a2
    lw a4, 0(a2)     # Load value at var2 into a4 (a4 = 20)

    # Arithmetic operations
    add a5, a0, a1   #a5 = a0 + a1  (10 + 20 = 30)
    sub a6, a1, a0   # a6 = a1 - a0  (20 - 10 = 10)
    
    # Logical operations
    and a7, a0, a1   # a7 = a0 & a1  (bitwise AND)
    or t0, a0, a1    # t0 = a0 | a1  (bitwise OR)
    xor t1, a0, a1   # t1 = a0 ^ a1  (bitwise XOR)
    
    # Shift operations
    slli t2, a0, 2   # t2 = a0 << 2  (Shift left by 2 bits) 1111 -> 1100
    srli t3, a0, 2   # t3 = a0 >> 2  (Logical shift right) 1111 -> 0011
    srai t4, a0, 2   # t4 = a0 >> 2  (Arithmetic shift right) can shift negative numbers (copies most significant bit)

    # Comparison
    slt t5, a0, a1   # t5 = (a0 < a1) ? 1 : 0  (10 < 20 → t5 = 1)
    sltu t6, a1, a0  # t6 = (a1 < a0 unsigned) ? 1 : 0  (unsigned comparison)

    # Branching
    beq a0, a1, equal_case  # If a0 == a1, jump to equal_case
    bne a0, a1, not_equal   # If a0 != a1, jump to not_equal
    blt a0, a1, less_case   # If a0 < a1, jump to less_case
    bge a1, a0, greater_case # If a1 >= a0, jump to greater_case
    
equal_case:
    li t6, 100   # t6 = 100 (this won't execute)
    j exit

not_equal:
    li t6, 200   # t6 = 200
    j exit

less_case:
    li t6, 300   # t6 = 300
    j exit

greater_case:
    li t6, 400   # t6 = 400
    j exit

    # Jump and Link (Function Call Simulation)
call_function:
    jal function   # Jump to function and save return address in ra
    j exit

function:
    addi sp, sp, -4   # Allocate stack space
    sw ra, 0(sp)      # Store return address
    li a0, 42         # Set return value
    lw ra, 0(sp)      # Restore return address
    addi sp, sp, 4    # Deallocate stack space
    ret               # Return to caller

exit:
    # Atomic operations (only in RV32A)
    la a0, var1       # Load address of var1
    li a1, 5
    amoadd.w a2, a1, (a0)  # var1 += 5 (Atomic addition)

    # Store result to memory
    sw a5, 0(a2)      # Store a5 into var1

    # System call to exit
    li a7, 10         # System call ID for exit

meByte: .byte 0x55
.skip 3               # Jump ahead 3 bytes (without this, the code will be misaligned)
.align 4              # Goes to the next address divisible by 4 (use only one of these)
meWord: .word 0x88776622
.data
var1:   .word 10    # Define a memory location var1 with value 10
var2:   .word 20    # Define a memory location var2 with value 20
    

Subroutines

Program counter points to the next instruction to be executed.

Different ways to call a function

 
call my_function # ra <- pc
my_function:
    

Jump (pseudo for

jal x0, my_function

 
j my_function # ra <- pc
my_function:
    

 
main:
jal ra, func  # Jump to func, save return address in ra
# Execution resumes here after func returns
func:
# Do something
ret  # Equivalent to `jalr x0, ra, 0`    
    

Return

 
my_function:
ret # pc <- ra
    

Stacks (LIFO)

Stacks grow downwards (from address 100 -> 1). Our stacks in this course start at 0x20000 (the first address is actually never used by the stack it is free to be used by anything else in the program).

Little endian: low order byte goes on low address.

# Initialize stack pointer
la sp, 0x20000
li t0, 0x12345678
# Push
addi sp, sp, -4 
sw t0, (sp)
# Pop
lw t1, (sp)     # t1 <- sp
addi sp, sp, 4  # sp <- sp + 4
# Now this is removed from the stack but is popped in t1
    

Where does 0x1234F678 go

Why do we need to push ra on the stack

To store multiple return addresses. Used when we need nested functions, recursive function calls, or generally want to avoid overwriting ra.

addi sp, sp, -4 
sw ra, (sp)      # Push ra onto the stack
                    # Order is important, can't do sw then addi because what if interrupt

.
.
call another_subroutine
.
.

lw ra, (sp)      # Pop ra from the stack
addi sp, sp, 4

ret
    

Registers (Calling Convention)

a0 ... a7: argument register

t0 ... t6: temporary

s0 ... s11: save registers

Memory Mapped I/O

LUTs (look up table) are used as small memory elements inside logic blocks to implement combinational logic functions.

Interval Timer (Delay)

.equ TIMER_BASE, 0xFF202000
.equ COUNTER_DELAY, 100000000
.equ LEDs, 0xFF200000

# Set up counter
_start: 
la t5, TIMER_BASE
sw zero, 0(t5)              # Clearing the TO bit in status register
li t0, COUNTER_DELAY        # Counter Start Register
srli t1, t0, 16             # Shift the upper 16 bits of the delay into the lower 16 bits of t1
sw t1, 0xc(t5)              # Put that into counter start high register 
# Set up control bit (turn on CONT and START)
li t0, 0b0110
sw t0, 4(t5)
la t6, LEDs
li t2, 1                    # Next of LED0
tloop: sw t2, (t6)          # Set LED0
        xori t2, t2, 1       # Invert bit 0 of t2
ploop: lw t0, (t5)          # Load "Timer Status Register"
        andi t0, t0, 1       # Isolate bit 0 -> t0 
        beqz t0, ploop
        sw zero, (t5)        # Reset t0
        j tloop
    

Edge Capture

signal ___---___ -> edge capture ______---. Basically captures the negative edge and stores it so we know the xyz signal condition has happened.

Writing 1 in an edge capture register bit erases it! Writing 0 keeps it as is

If we do edge capture with keys for example: Memory address 0xFF200050

 
la a1, edgecapture
lw s0, (a1)
andi s1, s0, 0b1111 # (isolate 4 bits of edge capture register)
li s1, 0b1111 # 1 erases the edge capture register to 0
sw s1, (a1)
    

Edge capture is how we actually interrupt something - write a 1 in bit 0 of interrupt mask register means whenever there's a 1 in the bit 0 of edge capture register, have that requests an interrupt. (Must turn off the edge capture bit - usually by user)

Polling

 
.equ KEY_BASE, 0xFF200050
la t0, KEY_BASE

# Polling Loop
poll: lw t1, (t0)
andi t1, t1, 0010   # bit mask 
beqz t1, poll 

# Arrive here when button is pressed
    

Interrupts

Make sure to pay attention to Lecture 14 (or whichever is Applying Interrupts to an Example I/O (KEYS for 2025))

Imagine it as adding another bus that is a "Interrupt Request Handler" -> Once an interrupt is caused then an action is taken, no continous mindless polling. Returns to the same instruction after working on the interrupt coming back to the same instruction as if nothing has happened (eg. no registers overwritten).

Registers:

• Step 1: Disable interrupts

  csrw mstatus, zero

• Step 2: Set up interrupt handler

  la t0, interrupt_handler_func   
  csrw mtvec, t0

• Step 3: Identify where the interrupt is coming from - tell microcontroller

  li t0, 0x40000 (IRQ18)
  csrs mie, t0

• Step 4: Tell peripheral to send interrupt

  la t0, 0xFF200050
  li t1, 0b1111 (if turning on a specific key, change this number)
  sw t1, 8(t0)

• Step 5: Turn on all interrupts again

  li t0, 0b1000
  csrw mstatus, t0

More detail (Interrupt Drive I/O)

Interrupts allow a processor to temporarily pause its current execution to handle external events, ensuring synchronization with peripherals.

Interrupt Sources

Interrupt Handling Steps

• The processor stops executing the current task.
• It jumps to the Interrupt Service Routine (ISR) to handle the event.
• Once the ISR completes, the processor resumes its previous task.
• Registers should be preserved using stack operations (push & pop) to avoid corrupting the main function's state.
• Interrupts must be explicitly enabled via an interrupt mask register (e.g., parallel port ITO bit).

In the diagram above, the things on the left are NOT addresses.

C Programming with Assembly

C is compiled to Assembly which is coded into numbers and space in memory that is coded into binary

            
# This is the program in assembly 
.global _start
.equ LEDs, 0xFF200000
.equ SW, 0xFF200040

_start: 
    la t0, LEDs
    la t1, SW
loop: 
    lw t2, (t1)
    sw t2, (t0)
    j loop
                
        

            
// This is the same program in C

int main (void){
    volatile int *LED_ptr = 0xFF200000;
    volatile int *SW_ptr = 0xFF200040;
    int value;

    while (1){
        value = *SW_ptr;
        *LED_ptr = value;
    }
}
                
        

Audio Signal Processing Chain

Music/Audio

Example: Guitar (Audio as sound pressure waves)

• Microphone: Converts sound waves to voltage over time.
• Inductor (coil), magnet, diaphragm: Create voltage from air pressure.

Signal Processing Steps

1. Microphone
   • Output: Voltage
2. Amplifier
   • Type: Operational Amplifier (Op-Amp)
   • Output: Amplified (bigger) voltage
3. ADC (Analog-to-Digital Converter)
   • Samples at specific duration (e.g., 10kHz sampling rate).
   • Converts time-varying voltage into a sequence of discrete (binary) values.
   • Output: Numbers encoded in binary at each sampling rate (e.g., 24 bits per sample).
   • Note: More bits mean higher accuracy but more expensive ADC.
   • Very Sophisticated
   • Takes in single wire, gives out 24 wires
4. Computer
   • Requires a memory-mapped interface.
   • Output: Memory storage of the sampled data.
5. Processor
   • Reads data from memory.
   • Output: Digital output (e.g., 24-bit data).
6. DAC (Digital-to-Analog Converter)
   • Converts digital data back to analog signals.
   • Not Very Sophisticated.
   • You start and end in Analog but signals are usually kept in Digital.
   • Takes 24 wires in, 1 wire out.
7. Speaker
   • Output: Sound

DE1-SoC Specific

• Includes a microphone input jack and a speaker output jack.
• Uses a CODEC chip connected to the jacks for amplification, ADC, and DAC.
• Samples sound input at 8 kHz - CODEC does this
• The processor might be busy and miss an input sample, (messing up the sound), or be late sending an output sample to the DAC
• For both above cases we need the input & output to be buffered -> with a hardware memory that acts as a queue (FIFO) (data struct but hardware) so a hardware FIFO.
• Consider the system that simply connects the microphone to the speaker through the computer
• Unless FIFO becomes full, processor isn't going to lose sound / malfunction
• FIFO deals with temporary absence by the processor

Person -> Microphone -> Amplifier -> ADC -> INPUT FIFO (does: store (not load)) -> 2<3<4<3<2<1 -> Computer -> OUTPUT FIFO -> DAC (output V)-> Amplifier -> Speaker

Buffer

• Computer memory may be too slow for real-time processing.
• Requires a memory buffer to hold onto samples temporarily.
• A queue (FIFO) (hardware) is used to manage the sample flow efficiently.
• This marks the transition from software to hardware.
• Input FIFO: load to addr, goes to ADC (same rate as sample rate ideally)
• Output FIFO: write to addr, goes from DAC

Memory-mapped input-output, we will be able to access registers to some address, same as previously discussed memory-mapped I/O. But this one is more complex. Processor, Memory, Audio -> cannot connect wi the specific memory-mapped registers that connect to input/output FIFOs fo the audio unit. 2 channels: 2 output FIFOs, 2 input FIFOs. Reading something takes it OUT of the FIFO.

Code

            32 bits memory address:
            0xFF203040: 9: WI, 8: RI, 3: CW, 2: CR, 1: WE, 0: RE control/status
            0xFF203044: 31-24: WSLC, 23-16: WSRC, 15-8: RALC, 7-0: RARC fifospace
            0xFF203048: 23-0: Left Data
            0xFF20304c: 23-0: Right Data
        

Left Data and Right Data

• If you loaded from these registers, it gets the next sample from the associated (left of right) FIFO, when that happens, that sample is removed from the input FIFO (so that you get the next one, when you next read)
• If you store/write into these registers, this sends that value as a sample into the left or right output FIFO.

FIFOspace

• RALC is how many of the left input FIFO entries are occupied
• RARC is how many of the right input FIFO entries are occupied
• WSLC is how many of the left input FIFO entries are empty
• WSRC is how many of the right input FIFO entries are empty

Control/Status

• Control: Write a '1' into CR (bit 2) cause the whole (both) input FIFO to be cleared.
• Control: Write a '1' into CW (bit 3) cause the whole (both) input FIFO to be cleared.
• Status: RI goes to '1' if the input FIFOs are ≥ 75% occupied.
• Status: WI goes to '1' if the output FIFOs are ≤ 25% occupied.
• Control: RE = 1 means request an interrupt when RI = 1
• Control: WE = 1 means request an interrupt when WI = 1

fun fact: this is where real hardware > cpulator (part2, 4 of lab 6)

for the project: a lot of samples, need the list of samples

int samples[] = {so, many, samples, so, many, samples, x20000}

Need to make sure that the sound is correctly sampled.

        #define AUDIO_BASE 0xFF203040
        
        int main (void){
            volatile int* audio_ptr = (int*) AUDIO_BASE;
            int left, right, fifospace;
            while(1){
                fifospace = *(audio_ptr + 1); //because pointer arithmetic: integer = 32 bits, next 1 is next 4 bits so 1 and not 4
            }
            if ((fifospace &0x000000FF)>0){ //right input fifo is not empty
                //load the 2 input channels if there is something there
                left = *(audio_ptr + 2); //same as lw t0, 8(t1)
                right = *(audio_ptr + 3);
                *(audio_ptr + 2) = left;
                *(audio_ptr + 3) = right;
            }
        }
        
    

VGA Display

• Pixels:
  • 5 bits: blue
  • 6 bits: green
  • 5 bits: red
  • All 1's: white
  • All 0's: black
• Coordinate System:

  Resolution: 320px (horizontal) x 240px (vertical)

  • Upper-left corner: (0, 0)
  • Upper-right corner: (319, 0)
  • Lower-left corner: (0, 239)
• How to map it to 1 dimension:
  • DE1SOC base for VGA: 0x08000000
  • Bit 0: Starting point
  • Next 9 bits (1-9): X
  • Next 8 bits (10-17): Y
  • Remaining bits (18-31): ignore
  • Shift your left and right address to get the pixel address (y << 10 and x << 1)

How does it actually work

• Processor → Frame Buffer (Memory) ↔ VGA Controller → Screen
• Software "draws" a picture into the frame buffer
• VGA Controller reads the frame buffer
• Controller renders the frame buffer onto the screen

Draw a Line (Bresenham's Algorithm)

• Color initial point
• Find slope
• Move x + 1
• y = y1 + slope * (x - x1)
• Round up or round down
• Move y + 1 when it crosses 45 degree slope (steep lines)

Animation

• Draw, wait, erase (draw black on the line), draw again
• VGA Controller renders something every 1/60th of a second
• When rendering is finished, it is called vertical sync
• Wait for vertical sync time to draw the next line

Double Buffering

• We need two frame buffers:
• One that is being used to do the rendering of the current frame → front buffer.
• One that is being used to draw the next frame → back buffer.
• Once the rendering is done and the drawing is done, we swap the addresses of the front buffer and the back buffer (VGA controller itself does it)
• Back buffer is a location in the memory. We write into the memory location where the back buffer is. That back buffer that stores it into memory BECOMES the front buffer and it gets rendered.
• Front and back registers borh start at 0x08000000 -> single buffering

The processor talks to the VGA controller

through these memory mapped registers:

Address	Register	Notes
0xFF203020	Front buffer address	default address 0x08000000, cannot change the address in this register (only changes with a swap)
0xFF203024	Back buffer address
0xFF203028
0xFF20302c	Status Register

• to use the second buffer must put a different address into back buffer register
• 3 types of memory (different range of addresses)
• FPGA memory
• DDR (D RAM)
• SRAM
• address must be in the range from 0x0->0x3FFFFFF (other addresses are not accessible to VGA controller).
• To cause a swap, do the following
• Software writes a "1" into a front buffer register
• It tells the controller to get ready to do the swap
• It causes the S bit of status register (bit 0) to be set to 1
• The swap doesn't happen right awat; controller waits till rendering is done
• That proint in time is called a vertical sync (vsync for short)
• Your code must poll the S but of the Status Register and wait for it to go back to 0 -> vsync and render done.

Function to wait for vsync

        void wait_for_vsync(){
            volatile int* fbuf = (int*) 0xFF203020; //base of VGA controller
            int status;
            *fbuf = 1; //start swap cycle per 1
            status = *(fbuf + 3); //read status register
            while ((status & 0x01)!=0){
                status = *(fbuf + 3);
            }
        }
    
    

SimProc

• Conditional Code Flags: These are used in conditional branching instructions
• z bit: zero flag, 1 if the result of a computation is 0, 0 otherwise
• n bit: negative flag, 1 if the result of a computation is negative, 0 otherwise
• v bit: overflow flag, 1 if the result of a computation is too large to fit in the destination, 0 otherwise
• c bit: carry flag, 1 if the result of a computation is too large to fit in the destination, 0 otherwise
• eg. add instruction: add r1, r2 (r1 += r2)
• Fetch the instruction
• Decode the instruction
• Execute the instruction
• Update the flags
• Store the result

• Instructions:
• memory instructions: load, store
• arithmetic instructions: add, sub, mul, div
• logical instructions: and, or, xor
• branch instructions: beq, bne, blt, bgt
• jump instructions: jmp, call, ret
• Registers:
• IR: Instruction Register
• MDR: Memory Data Register
• MAR: Memory Address Register
• PC: Program Counter
• SP: Stack Pointer
• SR: Status Register

GPUs (not in syllabus)

• CPUs are designed to do little steps. Modern CPUs are latency machines.
• SISD: Single Instruction, Single Data
• SIMD: Single Instruction, Multiple Data: every one of the 32 things have to do exactly the same thing
• SPMD: Single Program, Multiple Data: every one of the 32 things have to do different things
• MIMD: Multiple Instruction, Multiple Data: each core can do whatever it wants
• GPUs are optimized for SIMD operations.
• GPUs are optimized for parallel processing, floating point operations, memory bandwidth, texture mapping and shading.
• Computer Graphics: mesh (all triangles - why: triangles are the most basic polygon, can be used to form any shape) (asset, scene, camera)
• gpu has almost a vector processor like engine for rendering
• there is parallelism in cpu too, latency is the problem.
• tolerating stalls: when one core is waiting for something, other cores can still continue to work
• Independent Circuit Texture lets you do texture mapping in parallel.
• Specialized for floating point operations.
• Vector Architecture: 1024 cores operating in parallel.
• CUDA: Compute Unified Device Architecture
• OpenCL: Open Computing Language
• Direct Compute: DirectX extension for high performance computing on the GPU.
• Process:
• Allocate CPU data structure
• initial data on cpu
• allocate gpu data structure
• copy data from cpu to gpu
• define execution configuration
• run kernel (cuda function)

            // my first cuda program
            __global__ void arradd(float *a, float fade, int N){
                int i = blockIdx.x * blockDim.x + threadIdx.x;
                if (i < N) a[i] *= fade;
            }
            int main(){
                float *a, *d_a;
                int N = 1000000;
                a = (float*)malloc(N*sizeof(float));
                cudaMalloc(&d_a, N*sizeof(float));
                cudaMemcpy(d_a, a, N*sizeof(float), cudaMemcpyHostToDevice);
            }
            arradd<<<1, 1024>>>(d_a, 0.5f, N);
        

    

Citations